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general description the MAX19713 is an ultra-low-power, highly integrated mixed-signal analog front-end (afe) ideal for wideband communication applications operating in full-duplex (fd) mode. optimized for high dynamic performance and ultra-low power, the device integrates a dual 10-bit, 45msps receive (rx) adc; dual 10-bit, 45msps transmit (tx) dac; three fast-settling 12-bit aux-dac channels for ancillary rf front-end control; and a 10-bit, 333ksps housekeeping aux-adc. the typical operating power in fd mode is 91.8mw at a 45mhz clock frequency. the rx adcs feature 54db sinad and 72.2dbc sfdr at 5.5mhz input frequency with a 45mhz clock frequency. the analog i/q input amplifiers are fully differential and accept 1.024v p-p full-scale signals. typical i/q channel matching is ?.03 phase and ?.02db gain. the tx dacs feature 70.3dbc sfdr at f out = 2.2mhz and f clk = 45mhz. the analog i/q full-scale output volt- age range is ?00mv differential. the output dc com- mon-mode voltage is selectable from 0.71v to 1.06v. the i/q channel offset is adjustable to optimize radio lineup sideband/carrier suppression. typical i/q channel matching is ?.01db gain and ?.05 phase. two independent 10-bit parallel, high-speed digital buses used by the rx adc and tx dac allow full- duplex operation for frequency-division duplex applica- tions. the rx adc and tx dac can be disabled independently to optimize power management. a 3-wire serial interface controls power-management modes, the aux-dac channels, and the aux-adc channels. the MAX19713 operates on a single 2.7v to 3.3v analog supply and 1.8v to 3.3v digital i/o supply. the MAX19713 is specified for the extended (-40? to +85?) temperature range and is available in a 56-pin, thin qfn package. the selector guide at the end of the data sheet lists other pin-compatible versions in this afe family. for time-division duplex (tdd) applications, refer to the max19705?ax19708 afe family of products. applications features ? dual 10-bit, 45msps rx adc and dual 10-bit, 45msps tx dac ? ultra-low power 91.8mw at f clk = 45mhz, fd mode 79.2mw at f clk = 45mhz, slow rx mode 49.5mw at f clk = 45mhz, slow tx mode low-current standby and shutdown modes ? programmable tx dac common-mode dc level and i/q offset trim ? excellent dynamic performance snr = 54.1db at f in = 5.5mhz (rx adc) sfdr = 70.3dbc at f out = 2.2mhz (tx dac) ? three 12-bit, 1 s aux-dacs ? 10-bit, 333ksps aux-adc with 4:1 input mux and data averaging ? excellent gain/phase match 0.03 phase, 0.02db gain (rx adc) at f in = 5.5mhz ? multiplexed parallel digital i/o ? serial-interface control ? versatile power-control circuits shutdown, standby, idle, tx/rx disable ? miniature 56-pin thin qfn package (7mm x 7mm x 0.8mm) MAX19713 10-bit, 45msps, full-duplex analog front-end ________________________________________________________________ maxim integrated products 1 19-0529; rev 1; 9/06 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. e v a l u a t i o n k i t a v a i l a b l e ordering information part* pin-package pkg code MAX19713etn 56 thin qfn-ep** t5677-1 MAX19713etn+ 56 thin qfn-ep** t5677-1 * all devices are specified over the -40? to +85? operating range. ** ep = exposed paddle. + denotes lead-free package. functional diagram and selector guide appear at end of data sheet. top view MAX19713 thin qfn 15 17 16 18 19 20 21 22 23 24 25 26 27 28 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 ognd ov dd da0 da1 da2 da3 refn com refin qdp qdn v dd gnd idp idn v dd dac1 dac2 dac3 adc1 48 47 46 45 44 43 54 53 56 55 52 51 50 49 1 2 3 4 5 6 7 8 9 1011121314 42 41 40 39 38 37 36 35 34 33 32 31 30 29 gnd ad0 ad1 v dd qap qan v dd gnd clk gnd ian iap v dd refp da6 da5 da4 da7 da8 da9 dout din sclk v dd gnd v dd adc2 exposed paddle (gnd) cs/wake note: the pin 1 indicator is ??for lead-free devices. pin configuration wimax cpes 801.11a/b/g wlan voip terminals portable communication equipment
MAX19713 10-bit, 45msps, full-duplex analog front-end 2 _______________________________________________________________________________________ absolute maximum ratings stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress rating s only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specificatio ns is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. v dd to gnd, ov dd to ognd ..............................-0.3v to +3.6v gnd to ognd.......................................................-0.3v to +0.3v iap, ian, qap, qan, idp, idn, qdp, qdn, dac1, dac2, dac3 to gnd .....................-0.3v to v dd adc1, adc2 to gnd.................................-0.3v to (v dd + 0.3v) refp, refn, refin, com to gnd ...........-0.3v to (v dd + 0.3v) ad0?d9, da0?a9, sclk, din, cs /wake, clk, dout to ognd .........................-0.3v to (ov dd + 0.3v) continuous power dissipation (t a = +70?) 56-pin thin qfn-ep (derate 27.8mw/? above +70?) 2.22w thermal resistance ja ..................................................36?/w operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-60? to +150? lead temperature (soldering, 10s) .................................+300? electrical characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units power requirements analog supply voltage v dd 2.7 3.0 3.3 v output supply voltage ov dd 1.8 v dd v fd m od e: f c lk = 45m h z, f ou t = 2.2m h z on b oth d ac channel s; f i n = 5.5m h z on b oth ad c channel s; aux- d ac s on and at m i d scal e, aux- ad c o n 31.9 37 spi2-tx mode: f clk = 45mhz, f out = 2.2mhz on both dac channels; rx adc off; aux-dacs on and at midscale, aux- adc on 16.7 19 spi1-rx mode: f clk = 45mhz, f in = 5.5mhz on both adc channels; tx dac off (tx dac outputs at 0v); aux-dacs on and at midscale, aux-adc on 27.6 32 spi4-tx mode: f clk = 45mhz, f out = 2.2mhz on both dac channels; rx adc on (output tri-stated); aux-dacs on and at midscale, aux-adc on 31.0 36 spi3-rx mode: f clk = 45mhz, f in = 5.5mhz on both channels; tx dac on (tx dac outputs at midscale); aux-dacs on and at midscale, aux-adc on 30.2 35 v dd supply current standby mode: clk = 0 or ov dd ; aux-dacs on and at midscale, aux-adc on 3.3 5 ma
MAX19713 10-bit, 45msps, full-duplex analog front-end _______________________________________________________________________________________ 3 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units idle mode: f clk = 45mhz; aux-dacs on and at midscale, aux-adc on 12.4 15 ma v dd supply current shutdown mode: clk = 0 or ov dd , aux- adc off 0.5 5 ? fd m od e: f c lk = 45m h z, f ou t = 2.2m h z on b oth d ac channel s; f i n = 5.5m h z on b oth ad c channel s; aux- d ac s o n and at m i d scal e, aux- ad c o n 4.6 spi1-rx and spi3-rx modes: f clk = 45mhz, f in = 5.5mhz on both adc channels; dac input bus tri-stated; aux- dacs on and at midscale, aux-adc on 4.35 ma spi2-tx and spi4-tx modes: f clk = 45mhz, f out = 2.2mhz on both dac channels; adc output bus tri-stated; aux- dacs on and at midscale, aux-adc on 310 standby mode: clk = 0 or ov dd ; aux- dacs on and at midscale, aux-adc on 0.1 idle mode: f clk = 45mhz; aux-dacs on and at midscale, aux-adc on 73 ov dd supply current shutdown mode: clk = 0 or ov dd, aux- adc off 0.1 ? rx adc dc accuracy resolution 10 bits integral nonlinearity inl 1.25 lsb differential nonlinearity dnl ?.65 lsb offset error residual dc offset error -5 0.2 +5 %fs gain error includes reference error -5 0.7 +5 %fs dc gain matching -0.15 0.04 +0.15 db offset matching ?0 lsb gain temperature coefficient ?0 ppm/? offset (v dd ?%) ?.2 power-supply rejection gain (v dd ?%) ?.07 lsb rx adc analog input input differential range v id differential or single-ended inputs 0.512 v input common-mode voltage range v cm v dd / 2 v r in switched capacitor load 120 k input impedance c in 5pf
MAX19713 10-bit, 45msps, full-duplex analog front-end 4 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units rx adc conversion rate maximum clock frequency f clk (note 2) 45 mhz channel ia 5 data latency channel qa 5.5 clock cycles rx adc dynamic characteristics (note 3) f in = 5.5mhz 52.7 54.5 signal-to-noise ratio snr f in = 19.4mhz 54 db f in = 5.5mhz 52.4 54.3 signal-to-noise and distortion sinad f in = 19.4mhz 53.9 db f in = 5.5mhz 63 72.1 spurious-free dynamic range sfdr f in = 19.4mhz 76.3 dbc f in = 5.5mhz -69.4 -61 total harmonic distortion thd f in = 19.4mhz -71.3 dbc f in = 5.5mhz -73.7 third-harmonic distortion hd3 f in = 19.4mhz -76.3 dbc intermodulation distortion imd f in1 = 1.8mhz, a in1 = -7dbfs; f in2 = 1.0mhz, a in2 = -7dbfs -69 dbc third-order intermodulation distortion im3 f in1 = 1.8mhz, a in1 = -7dbfs; f in2 = 1.0mhz, a in2 = -7dbfs -72 dbc aperture delay 3.5 ns aperture jitter 2ps rms overdrive recovery time 1.5x full-scale input 2 ns rx adc interchannel characteristics crosstalk rejection f in x ,y = 5.5m h z, a in x ,y = - 0.5d bfs , f in y ,x = 1.8m h z, a in y ,x = - 0.5d bfs ( n ote 4) -88 db amplitude matching f in = 5.5mhz, a in = -0.5dbfs (note 5) ?.02 db phase matching f in = 5.5mhz, a in = -0.5dbfs (note 5) ?.03 d eg r ees tx dac dc accuracy resolution n 10 bits integral nonlinearity inl 0.35 lsb differential nonlinearity dnl guaranteed monotonic (note 6) -0.7 ?.2 +0.7 lsb residual dc offset v os -4 ?.1 +4 mv full-scale gain error -40 +40 mv
MAX19713 10-bit, 45msps, full-duplex analog front-end _______________________________________________________________________________________ 5 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units tx dac dynamic performance dac conversion rate f clk (note 2) 45 mhz in-band noise density n d f out = 2.2mhz -129 d bfs /h z third-order intermodulation distortion im3 f out1 = 2mhz, f out2 = 2.2mhz -82 dbc glitch impulse 10 pv s spurious-free dynamic range to nyquist sfdr f out = 2.2mhz 61.5 70.3 dbc total harmonic distortion to nyquist thd f out = 2.2mhz -68.1 -60.5 dbc signal-to-noise ratio to nyquist snr f out = 2.2mhz 56.1 db tx dac interchannel characteristics i-to-q output isolation f outx,y = 500khz, f outy,x = 620khz 85 db gain mismatch between i and q channels measured at dc -0.4 ?.01 +0.4 db phase mismatch between i and q channels f out = 2.2mhz ?.05 d eg r ees differential output impedance 800 tx dac analog output full-scale output voltage v fs ?00 mv bits cm1 = 0, cm0 = 0 (default) 1.01 1.06 1.11 bits cm1 = 0, cm0 = 1 0.88 0.94 1.00 bits cm1 = 1, cm0 = 0 0.75 0.82 0.90 output common-mode voltage v comd bits cm1 = 1, cm0 = 1 0.62 0.71 0.81 v rx adc?x dac interchannel characteristics receive transmit isolation ad c : f i n i = f i n q = 5.5m h z, d ac : f ou t i = f ou t q = 2.2m h z 85 db auxiliary adcs ( adc1, adc2 ) resolution n 10 bits ad1 = 0 (default) 2.048 full-scale reference v ref ad1 = 1 v dd v analog input range 0 to v ref v analog input impedance measured at dc 500 k input-leakage current m easur ed at unsel ected i np ut fr om 0 to v re f ?.1 ? gain error ge includes reference error, ad1 = 0 -5 +5 %fs zero-code error ze 2 mv differential nonlinearity dnl ?.6 lsb
MAX19713 10-bit, 45msps, full-duplex analog front-end 6 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units integral nonlinearity inl 0.6 lsb supply current 210 ? auxiliary dacs (dac1, dac2, dac3) resolution n 12 bits integral nonlinearity inl from code 100 to code 4000 ?.25 lsb differential nonlinearity dnl guaranteed monotonic over code 100 to code 4000 (note 6) -1.0 ?.65 +1.2 lsb output-voltage low v ol r l > 200k 0.2 v output-voltage high v oh r l > 200k 2.57 v dc output impedance dc output at midscale 4 settling time from code 1024 to code 3072, within ?0 lsb 1s glitch impulse from code 0 to code 4095 24 nv s rx adc?x dac timing characteristics clk rise to channel-i output data valid t doi figure 3 (note 6) 5.5 8.2 12.5 ns clk fall to channel-q output data valid t doq figure 3 (note 6) 6.5 9.5 13.6 ns i- d ac d ata to c lk fal l s etup ti m et d s i fi g ur e 5 ( n ote 6) 10 ns q-dac data to clk rise setup time t dsq figure 5 (note 6) 10 ns clk fall to i-dac data hold time t dhi figure 5 (note 6) 0 ns clk rise to q-dac data hold time t dhq figure 5 (note 6) 0 ns clk duty cycle 50 % clk duty-cycle variation ?0 % digital output rise/fall time 20% to 80% 2.4 ns serial-interface timing characteristics (figures 6 and 8, note 6) falling edge of cs /wake to rising edge of first sclk time t css 10 ns din to sclk setup time t ds 10 ns din to sclk hold time t dh 0ns sclk pulse-width high t ch 25 ns sclk pulse-width low t cl 25 ns sclk period t cp 50 ns sclk to cs /wake setup time t cs 10 ns cs /wake high pulse width t csw 80 ns cs /wake high to dout active high t csd bit ad0 set 200 ns
MAX19713 10-bit, 45msps, full-duplex analog front-end _______________________________________________________________________________________ 7 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units cs /wake high to dout low (aux-adc conversion time) t conv bit ad0 set, no averaging, f clk = 45mhz, clk divider = 16 4.3 s dout low to cs /wake setup time t dcs bit ad0, ad10 set 200 ns sclk low to dout data out t cd bit ad0, ad10 set 14.5 ns cs /wake high to dout high impedance t chz bit ad0, ad10 set 200 ns mode-recovery timing characteristics (figure 7) from shutdown to rx mode, adc settles to within 1db sinad 500 from shutdown to tx mode, dac settles to within 10 lsb error 26.4 from aux-adc enable to aux-adc start conversion 10 from shutdown to aux-dac output valid 28 shutdown wake-up time t wake , sd from shutdown to fd mode, adc settles to within 1db sinad, dac settles to within 10 lsb error 500 ? fr om i d l e to rx m od e w i th c lk p r esent d ur i ng i d l e, ad c settl es to w i thi n 1d b s in ad 3.7 from idle to tx mode with clk present during idle, dac settles to 10 lsb error 5.1 idle wake-up time (with clk) t wake , st0 from idle to fd mode, adc settles to within 1db sinad, dac settles to within 10 lsb error 5.1 ? from standby to rx mode, adc settles to within 1db sinad 3.8 from standby to tx mode, dac settles to 10 lsb error 24.4 standby wake-up time t wake , st1 from standby to fd mode, adc settles to within 1db sinad, dac settles to within 10 lsb error 24.4 ? enable time from tx to rx, fast mode t enable , rx adc settles to within 1db sinad 0.1 s e nab l e ti m e fr om rx to tx, fast m od e t enable , tx dac settles to within 10 lsb error 0.1 ? enable time from tx to rx, slow mode t enable , rx adc settles to within 1db sinad 3.7 s
MAX19713 10-bit, 45msps, full-duplex analog front-end 8 _______________________________________________________________________________________ electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) parameter symbol conditions min typ max units e nab l e ti m e fr om rx to tx, s l ow m od e t enable , tx dac settles to within 10 lsb error 4.9 ? internal reference (v refin = v dd ; v refp , v refn , v com levels are generated internally) positive reference v refp - v com 0.256 v negative reference v refn - v com -0.256 v common-mode output voltage v com v dd / 2 - 0.15 v dd / 2 v dd / 2 + 0.15 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma differential reference output v ref v refp - v refn +0.490 +0.512 +0.534 v differential reference temperature coefficient reftc ?0 ppm/? buffered external reference (external v refin = 1.024v applied; v refp , v refn , v com levels are generated internally) reference input voltage v refin 1.024 v differential reference output v diff v refp - v refn 0.512 v common-mode output voltage v com v dd / 2 v maximum refp/refn/com source current i source 2ma maximum refp/refn/com sink current i sink 2ma refin input current -0.7 ? refin input resistance 500 k digital inputs (clk, sclk, din, cs /wake, da9?a0) input high threshold v inh 0.7 x ov dd v input low threshold v inl 0.3 x ov dd v clk, sclk, din, cs /wake = ognd or ov dd -1 +1 da9?a0 = ov dd -1 +1 input leakage di in da9?a0 = ognd -5 +5 ? input capacitance dc in 5pf digital outputs (ad9?d0, dout) output-voltage low v ol i sink = 200? 0.2 x ov dd v output-voltage high v oh i source = 200? 0.8 x ov dd v tri-state leakage current i leak -1 +1 ? tri-state output capacitance c out 5pf
MAX19713 10-bit, 45msps, full-duplex analog front-end _______________________________________________________________________________________ 9 electrical characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, c l < 5pf on all aux-dac outputs, t a = t min to t max , unless otherwise noted. typical values are at t a = +25?.) (note 1) note 1: specifications from t a = +25? to +85? guaranteed by production tests. specifications at t a < +25? guaranteed by design and characterization. note 2: the minimum clock frequency (f clk ) for the MAX19713 is 7.5mhz (typ). the minimum aux-adc sample rate clock frequency (a clk ) is determined by f clk and the chosen aux-adc clock-divider value. the minimum aux-adc a clk > 7.5mhz / 128 = 58.6khz. the aux-adc conversion time does not include the time to clock the serial data out of dout. the maximum con- version time (for no averaging, navg = 1) will be t conv (max) = (12 x 1 x 128) / 7.5mhz = 205?. note 3: snr, sinad, sfdr, hd3, and thd are based on a differential analog input voltage of -0.5dbfs referenced to the amplitude of the digital outputs. sinad and thd are calculated using hd2 through hd6. note 4: crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the sec- ond channel. ffts are performed on each channel. the parameter is specified as the power ratio of the first and second channel fft test tones. note 5: amplitude and phase matching are measured by applying the same signal to each channel, and comparing the two output signals using a sine-wave fit. note 6: guaranteed by design and characterization. typical operating characteristics (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) rx adc channel-ia fft plot (8192 samples) MAX19713 toc01 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 5 4 2 3 6 0 5 10 15 20 fundamental f in = 13.024292mhz a in = -0.488dbfs sinad = 53.763db snr = 54.003db sfdr = 71.6dbc thd = -66.46dbc rx adc channel-qa fft plot ( 8 192 samples) MAX19713 toc02 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 5 4 2 3 6 fundamental 0 5 10 15 20 f in = 13.024292mhz a in = -0.48dbfs sinad = 54.216db snr = 54.302db sfdr = 76dbc thd = -71.311dbc rx adc channel-ia two-tone fft plot MAX19713 toc03 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 f in1 = 1.7605591mhz f in2 = 1.8484497mhz a in1 = a in2 = -7dbfs imd = -65dbc 2f in1 - f in2 f in1 f in2 2f in2 - f in1 0 5 10 15 20
MAX19713 10-bit, 45msps, full-duplex analog front-end 10 ______________________________________________________________________________________ rx adc channel-qa two-tone fft plot MAX19713 toc04 frequency (mhz) amplitude (dbfs) -90 -80 -70 -60 -50 -40 -30 -20 -10 0 -100 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 f in1 = 1.7605591mhz f in2 = 1.8484497mhz a in1 = a in2 = -7dbfs imd = -66dbc 2f in1 - f in2 2f in2 - f in1 f in2 f in1 rx adc signal-to-noise ratio vs. analog input frequency MAX19713 toc05 analog input frequency (mhz) snr (db) 80 60 20 40 51 52 53 54 55 57 56 50 0 100 70 50 10 30 90 qa ia rx adc signal-to-noise and distortion ratio vs. analog input frequency MAX19713 toc06 analog input frequency (mhz) sinad (db) 80 60 20 40 51 52 53 54 55 57 56 50 0 100 70 50 10 30 90 qa ia rx adc total harmonic distortion vs. analog input frequency MAX19713 toc07 analog input frequency (mhz) -thd (dbc) 80 60 20 40 55 60 65 70 75 85 90 80 50 0 100 70 50 10 30 90 qa ia rx adc spurious-free dynamic range vs. analog input frequency MAX19713 toc08 analog input frequency (mhz) sfdr (dbc) 80 60 20 40 55 60 65 70 75 85 90 80 50 0 100 70 50 10 30 90 qa ia rx adc signal-to-noise ratio vs. analog input amplitude MAX19713 toc09 analog input amplitude (dbfs) snr (db) -5 -25 -20 25 30 35 40 45 55 60 50 20 -30 0 -10 -15 qa ia f in = 13.057251mhz typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) rx adc signal-to-noise and distortion ratio vs. analog input amplitude MAX19713 toc10 analog input amplitude (dbfs) sinad (db) -5 -25 -20 25 30 35 40 45 55 60 50 20 -30 0 -10 -15 qa ia f in = 13.057251mhz rx adc total harmonic distortion vs. analog input amplitude MAX19713 toc11 analog input amplitude (dbfs) -thd (dbc) -5 -25 -20 35 40 45 50 55 65 70 75 80 60 30 -30 0 -10 -15 qa ia f in = 13.057251mhz
MAX19713 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 11 rx adc spurious-free dynamic range vs. analog input amplitude MAX19713 toc12 analog input amplitude (dbfs) sfdr (dbc) -5 -25 -20 35 40 45 50 55 65 70 75 80 60 30 -30 0 -10 -15 qa ia f in = 13.057251mhz rx adc signal-to-noise ratio vs. sampling frequency MAX19713 toc13 sampling frequency (mhz) snr (db) 30 10 15 52.5 53.0 53.5 54.0 54.5 55.5 56.0 56.5 57.0 55.0 52.0 545 25 40 35 20 qa ia f in = 13.024292mhz rx adc signal-to-noise and distortion ratio vs. sampling frequency MAX19713 toc14 sampling frequency (mhz) sinad (db) 30 10 15 52.5 53.0 53.5 54.0 54.5 55.5 56.0 56.5 57.0 55.0 52.0 545 25 40 35 20 qa ia f in = 13.024292mhz rx adc total harmonic distortion vs. sampling frequency MAX19713 toc15 sampling frequency (mhz) -thd (dbc) 30 10 15 60 65 70 75 80 85 55 545 25 40 35 20 qa ia f in = 13.024292mhz rx adc spurious-free dynamic range vs. sampling frequency MAX19713 toc16 sampling frequency (mhz) sfdr (dbc) 30 10 15 65 60 70 75 80 85 90 55 545 25 40 35 20 qa ia f in = 13.024292mhz rx adc signal-to-noise ratio vs. clock duty cycle MAX19713 toc17 clock duty cycle (%) snr (db) 45 47.5 45.0 50.0 55.0 52.5 57.5 62.5 60.0 65.0 40.0 42.5 40 60 50 55 qa ia f in = 13.024292mhz rx adc signal-to-noise and distortion ratio vs. clock duty cycle MAX19713 toc18 clock duty cycle (%) sinad (db) 45 47.5 45.0 50.0 55.0 52.5 57.5 62.5 60.0 65.0 40.0 42.5 40 60 50 55 qa ia f in = 13.024292mhz typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
MAX19713 10-bit, 45msps, full-duplex analog front-end 12 ______________________________________________________________________________________ rx adc gain error vs. temperature temperature ( c) gain error (%fs) MAX19713 toc22 -40 -15 10 35 60 85 0 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 qa ia rx adc total harmonic distortion vs. clock duty cycle MAX19713 toc19 clock duty cycle (%) -thd (dbc) 45 50 45 55 60 70 65 80 75 85 95 90 100 30 35 40 40 60 50 55 qa ia f in = 13.024292mhz rx adc spurious-free dynamic range vs. clock duty cycle MAX19713 toc20 clock duty cycle (%) sfdr (dbc) 45 50 45 55 60 70 65 80 75 85 95 90 100 30 35 40 40 60 50 55 qa ia f in = 13.024292mhz rx adc offset error vs. temperature temperature ( c) offset error (%fs) MAX19713 toc21 -40 -15 10 35 60 85 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 qa ia tx dac spurious-free dynamic range vs. sampling frequency MAX19713 toc23 sampling frequency (mhz) sfdr (dbc) 15 65 70 80 75 85 90 55 60 545 25 35 10 40 20 30 f out = f clk / 10 qd id tx dac spurious-free dynamic range vs. output frequency MAX19713 toc24 output frequency (mhz) sfdr (dbc) 4 55 60 70 65 75 80 45 50 022 812 214 610 1820 16 qd id tx dac spurious-free dynamic range vs. output amplitude MAX19713 toc25 output amplitude (dbfs) sfdr (dbc) -25 40 50 70 60 80 90 30 -30 0 -20 -15 -10 -5 qd id f out = 5.498mhz tx dac channel-id spectral plot MAX19713 toc26 frequency (mhz) amplitude (dbfs) -70 -40 -20 -30 -60 -50 -10 0 -90 -80 f out = 5.498mhz hd3 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 tx dac channel-qd spectral plot MAX19713 toc27 frequency (mhz) amplitude (dbfs) -70 -40 -20 -30 -60 -50 -10 0 -90 -80 f out = 5.498mhz hd3 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.)
MAX19713 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 13 tx dac channel-id two-tone spectral plot MAX19713 toc28 frequency (mhz) amplitude (dbfs) -70 -40 -20 -30 -60 -50 -10 0 -90 -80 f out1 = 4mhz, f out2 = 4.5mhz 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 tx dac channel-qd two-tone spectral plot MAX19713 toc29 frequency (mhz) amplitude (dbfs) -70 -40 -20 -30 -60 -50 -10 0 -90 -80 f out1 = 4mhz, f out2 = 4.5mhz 0 2.5 5.0 7.5 10.0 12.5 15.0 17.5 20.0 22.5 supply current vs. sampling frequency MAX19713 toc30 sampling frequency (mhz) i vdd (ma) 15 25 30 35 40 15 20 545 25 35 10 40 20 30 f in = 13.024292mhz, f out = 5.498mhz, fd mode rx adc integral nonlinearity digital output code inl (lsb) MAX19713 toc31 0 128 256 384 512 640 768 896 1024 -1.50 -1.25 -1.00 -0.75 -0.50 -0.25 0 0.25 0.50 0.75 1.00 1.25 1.50 rx adc differential nonlinearity digital output code dnl (lsb) MAX19713 toc32 0 128 256 384 512 640 768 896 1024 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 tx dac differential nonlinearity digital input code dnl (lsb) MAX19713 toc34 0 128 256 384 512 640 768 896 1024 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 reference output voltage vs. temperature temperature ( c) v refp - v refn (v) MAX19713 toc35 -40 -15 10 35 60 85 0.500 0.505 0.510 0.515 0.520 v refp - v refn aux-dac integral nonlinearity digital input code inl (lsb) MAX19713 toc36 0 512 1024 1536 2048 2560 3072 3584 4096 -2.0 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 2.0 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) tx dac integral nonlinearity digital input code inl (lsb) MAX19713 toc33 0 128 256 384 512 640 768 896 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8
MAX19713 10-bit, 45msps, full-duplex analog front-end 14 ______________________________________________________________________________________ aux-dac differential nonlinearity digital input code dnl (lsb) MAX19713 toc37 0 512 1024 1536 2048 2560 3072 3584 4096 -1.0 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 1.0 aux-adc integral nonlinearity digital output code inl (lsb) MAX19713 toc38 0 128 256 384 512 640 768 896 1024 -1.5 -1.0 -0.5 0 0.5 1.0 1.5 aux-adc differential nonlinearity digital output code dnl (lsb) MAX19713 toc39 0 128 256 384 512 640 768 896 1024 -0.8 -0.6 -0.4 -0.2 0 0.2 0.4 0.6 0.8 aux-dac output voltage vs. output source current MAX19713 toc40 output source current (ma) output voltage (v) 0.01 1.5 2.0 2.5 3.0 0 1.0 0.5 0.001 100 10 0.1 1 aux-dac output voltage vs. output sink current MAX19713 toc41 output sink current (ma) output voltage (v) 0.01 1.5 2.0 2.5 3.0 0 1.0 0.5 0.001 100 10 0.1 1 typical operating characteristics (continued) (v dd = 3v, ov dd = 1.8v, internal reference (1.024v), c l 10pf on all digital outputs, f clk = 45mhz (50% duty cycle), rx adc input amplitude = -0.5dbfs, tx dac output amplitude = 0dbfs, cm1 = 0, cm0 = 0, differential rx adc input, differential tx dac output, c refp = c refn = c com = 0.33?, t a = +25?, unless otherwise noted.) aux-dac settling time MAX19713 toc42 aux-dac output cs/wake 1v/div 500mv/div 400ns/div step from code 1024 to code 3072
MAX19713 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 15 pin description detailed description the MAX19713 integrates a dual, 10-bit rx adc and a dual, 10-bit tx dac while providing ultra-low power and high dynamic performance at 45msps conversion rate. the rx adc analog input amplifiers are fully differ- ential and accept 1.024v p-p full-scale signals. the tx dac analog outputs are fully differential with ?00mv full-scale output, selectable common-mode dc level, and adjustable channel id?d offset trim. pin name function 1 refp positive reference voltage input terminal. bypass with a 0.33? capacitor to gnd as close to refp as possible. 2, 8, 11, 39, 41, 47, 51 v dd analog supply voltage. bypass v dd to gnd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 3 iap channel-ia positive analog input. for single-ended operation, connect signal source to iap. 4 ian channel-ia negative analog input. for single-ended operation, connect ian to com. 5, 7, 12, 40, 50 gnd analog ground. connect all gnd pins to ground plane. 6 clk conversion clock input. clock signal for both receive adcs and transmit dacs. 9 qan channel-qa negative analog input. for single-ended operation, connect qan to com. 10 qap channel-qa positive analog input. for single-ended operation, connect signal source to qap. 13?2 ad0?d9 receive adc digital outputs. ad9 is the most significant bit (msb) and ad0 is the least significant bit (lsb). 23 ognd output-driver ground 24 ov dd output-driver power supply. supply range from +1.8v to v dd . bypass ov dd to ognd with a combination of a 2.2? capacitor in parallel with a 0.1? capacitor. 25?4 da0?a9 transmit dac digital inputs. da9 is the most significant bit (msb) and da0 is the least significant bit (lsb). da0?a9 are internally pulled up to ov dd. 35 dout aux-adc digital output 36 din 3-wire serial-interface data input. data is latched on the rising edge of sclk. 37 sclk 3-wire serial-interface clock input 38 cs /wake 3-wire serial-interface chip-select/wake input. when the MAX19713 is in shutdown, cs /wake controls the wake-up function. see the wake-up function section. 42 adc2 selectable auxiliary adc analog input 2 43 adc1 selectable auxiliary adc analog input 1 44 dac3 auxiliary dac3 analog output (v out = 0 at power-up) 45 dac2 auxiliary dac2 analog output (v out = 0 at power-up) 46 dac1 auxiliary dac1 analog output (afc dac, v out = 1.1v at power-up) 48 idn tx dac channel-id differential negative output 49 idp tx dac channel-id differential positive output 52 qdn tx dac channel-qd differential negative output 53 qdp tx dac channel-qd differential positive output 54 refin reference input. connect to v dd for internal reference. 55 com common-mode voltage i/o. bypass com to gnd with a 0.33? capacitor. 56 refn negative reference voltage input terminal. rx adc conversion range is ?v refp - v refn ). bypass refn to gnd with a 0.33? capacitor. ep exposed paddle. exposed paddle is internally connected to gnd. connect ep to the gnd plane.
MAX19713 10-bit, 45msps, full-duplex analog front-end 16 ______________________________________________________________________________________ figure 1. rx adc internal t/h circuits the MAX19713 integrates three 12-bit auxiliary dacs (aux-dacs) and a 10-bit, 333ksps auxiliary adc (aux- adc) with 4:1 input multiplexer. the aux-dac channels feature 1? settling time for fast agc, vga, and afc level setting. the aux-adc features data averaging to reduce processor overhead and a selectable clock- divider to program the conversion rate. the MAX19713 includes a 3-wire serial interface to con- trol operating modes and power management. the seri- al interface is spi and microwire compatible. the MAX19713 serial interface selects shutdown, idle, standby, fd, transmit (tx), and receive (rx) modes, as well as controls aux-dac and aux-adc channels. the MAX19713 features two independent, high-speed, 10-bit buses for the rx adc and tx dac, which allow full-duplex (fd) operation for frequency-division duplex applications. each bus can be disabled to optimize power management through the 3-wire interface. the MAX19713 operates from a single 2.7v to 3.3v analog supply and a 1.8v to 3.3v digital supply. dual 10-bit rx adc the adc uses a seven-stage, fully differential, pipelined architecture that allows for high-speed conversion while minimizing power consumption. samples taken at the inputs move progressively through the pipeline stages every half clock cycle. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel ia and 5.5 clock cycles for channel qa. the adc full-scale analog input range is ? ref with a v dd / 2 (?.8v) common-mode input range. v ref is the difference between v refp and v refn . see the reference configurations section for details. input track-and-hold (t/h) circuits figure 1 displays a simplified diagram of the rx adc input track-and-hold (t/h) circuitry. both adc inputs (iap, qap, ian, and qan) can be driven either differen- tially or single-ended. match the impedance of iap and s3b s3a com s5b s5a qap qan s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com hold hold clk internal nonoverlapping clock signals track track s2a s2b s3b s3a com s5b s5a iap ian s1 out out c2a c2b s4c s4a s4b c1b c1a internal bias internal bias com s2a s2b MAX19713 microwire is a trademark of national semiconductor corp. spi is a trademark of motorola, inc.
MAX19713 ian, as well as qap and qan, and set the input signal common-mode voltage within the v dd / 2 (?.8v) rx adc range for optimum performance. rx adc system timing requirements figure 3 shows the relationship between the clock, ana- log inputs, and the resulting output data. channels ia and qa are sampled on the rising edge of the clock sig- nal (clk) and the resulting data is multiplexed at the ad0?d9 outputs. channel ia data is updated on the ris- ing edge and channel qa data is updated on the falling edge of clk. including the delay through the output latch, the total clock-cycle latency is 5 clock cycles for channel ia and 5.5 clock cycles for channel qa. digital output data (ad0?d9) ad0?d9 are the rx adc digital logic outputs of the MAX19713. the logic level is set by ov dd from 1.8v to v dd . the digital output coding is offset binary (table 1). keep the capacitive load on the digital outputs ad0?d9 as low as possible (< 15pf) to avoid large digital currents feeding back into the analog portion of the MAX19713 and degrading its dynamic performance. buffers on the digital outputs isolate the outputs from heavy capacitive loads. adding 100 resistors in series with the digital out- puts close to the MAX19713 will help improve adc per- formance. refer to the MAX19713evkit schematic for an example of the digital outputs driving a digital buffer through 100 series resistors. during shdn, idle, stby, spi2, and spi4 states, digital outputs ad0?d9 are tri-stated. dual 10-bit tx dacs the dual 10-bit digital-to-analog converters (tx dacs) operate with clock speeds up to 45mhz. the tx dac digital inputs, da0?a9, are multiplexed on a single 10-bit transmit bus. the voltage reference determines the tx dac full-scale voltage at idp, idn and qdp, qdn analog outputs. see the reference configurations section for setting the reference voltage. figure 2. rx adc transfer function input voltage (lsb) -1 -510 -509 1024 2 x v ref 1 lsb = v ref = v refp - v refn v ref v ref v ref v ref 0+ 1 -511 +510 +512 +511 -512 +509 (com) (com) o f f s e t b i n a r y o u t p u t c o d e ( l s b ) 00 0000 0000 00 0000 0001 00 0000 0010 00 0000 0011 11 1111 1111 11 1111 1110 11 1111 1101 01 1111 1111 10 0000 0000 10 0000 0001 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 17 table 1. rx adc output codes vs. input voltage differential input voltage differential input ( lsb ) offset binary ( ad0?d9 ) output decimal code v ref x 512/512 511 (+full scale - 1 lsb) 11 1111 1111 1023 v ref x 511/512 510 (+full scale - 2 lsb) 11 1111 1110 1022 v ref x 1/512 +1 10 0000 0001 513 v ref x 0/512 0 (bipolar zero) 10 0000 0000 512 -v ref x 1/512 -1 01 1111 1111 511 -v ref x 511/512 -511 (-full scale + 1 lsb) 00 0000 0001 1 -v ref x 512/512 -512 (-full scale) 00 0000 0000 0
MAX19713 10-bit, 45msps, full-duplex analog front-end 18 ______________________________________________________________________________________ figure 3. rx adc system timing diagram t doq t cl t ch t clk t doi 5 clock-cycle latency (ia) 5.5 clock-cycle latency (qa) d0?9 d0q d1i d1q d2i d2q d3i d3q d4i d4q d5i d5q d6i d6q ia qa clk table 2. tx dac output voltage vs. input codes (internal reference mode v refdac = 1.024v, external reference mode v refdac = v refin , v fs = 400 for 800mv p-p full scale) the tx dac outputs (idn, idp, qdn, qdp) are biased at an adjustable common-mode dc level and designed to drive a differential input stage with 70k input imped- ance. this simplifies the analog interface between rf quadrature upconverters and the MAX19713. many rf upconverters require a 0.71v to 1.06v common-mode bias. the MAX19713 common-mode dc bias eliminates discrete level-setting resistors and code-generated level shifting while preserving the full dynamic range of each tx dac. the tx dac differential analog outputs can- not be used in single-ended mode because of the internally generated common-mode dc level. table 2 shows the tx dac output voltage vs. input codes. table 10 shows the selection of dc common-mode levels. see figure 4 for an illustration of the tx dac analog output levels. the tx dac also features an independent dc offset trim on each id?d channel. this feature is configured through the spi interface. the dc offset correction is used to optimize sideband and carrier suppression in the tx signal path (see table 9). differential output voltage ( v ) offset binary (da0?a9) input decimal code 11 1111 1111 1023 11 1111 1110 1022 10 0000 0001 513 10 0000 0000 512 01 1111 1111 511 00 0000 0001 1 00 0000 0000 0 v v fs refdac 1024 1023 1023 () v v fs refdac 1024 1021 1023 () v v fs refdac 1024 3 1023 () v v fs refdac 1024 1 1023 () v v fs refdac 1024 1 1023 () ? v v fs refdac 1024 1021 1023 () ? v v fs refdac 1024 1023 1023 () ?
MAX19713 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 19 figure 5. tx dac system timing diagram t dsq t dsi q: n - 2 i: n - 1 d0?9 clk id qd q: n - 1 i: n q: n i: n + 1 n - 2 n - 1 n n - 2 n - 1 n t dhq t dhi figure 4. tx dac common-mode dc level at idn, idp or qdn, qdp differential outputs 0 full scale = 1.26v v comd = 1.06v zero scale = 0.86v 0v common-mode level example: tx rfic input requirements ?dc common-mode bias = 0.9v (min), 1.3v (typ) ?baseband input = 400mv dc-coupled 90 MAX19713 select cm1 = 0, cm0 = 0 v comd = 1.06v v fs = 400mv tx dac ch-id tx dac ch-qd
MAX19713 10-bit, 45msps, full-duplex analog front-end 20 ______________________________________________________________________________________ tx dac timing figure 5 shows the relationship among the clock, input data, and analog outputs. channel id data is latched on the falling edge of the clock signal, and channel qd data is latched on the rising edge of the clock signal, at which point both id and qd outputs are simultaneously updated. 3-wire serial interface and operation modes the 3-wire serial interface controls the MAX19713 oper- ation modes as well as the three 12-bit aux-dacs and the 10-bit aux-adc. upon power-up, program the MAX19713 to operate in the desired mode. use the 3- wire serial interface to program the device for shutdown, idle, standby, fd, rx, tx, aux-dac controls, or aux-adc conversion. a 16-bit data register sets the mode control as shown in table 3. the 16-bit word is composed of four control bits (a3?0) and 12 data bits (d11?0). data is shifted in msb first (d11) and lsb last (a0) for- mat. table 4 shows the MAX19713 power-management modes. table 5 shows the spi-controlled tx, rx, and fd modes. the serial interface remains active in all modes. spi register description program the control bits, a3?0, in the register as shown in table 3 to select the operating mode. modify a3?0 bits to select from enable-16, aux-dac1, aux-dac2, aux-dac3, ioffset, qoffset, comsel, aux-adc, enable-8, and wakeup-sel modes. enable-16 is the default operating mode (see table 6). this mode allows for shutdown, idle, and standby states as well as switching between fast, slow, rx and tx modes. tables 4 and 5 show the required spi settings for each mode. in enable-16 mode, the aux-dacs have independent control bits e4, e5, and e6, bit e9 enables the aux-adc. table 7 shows the auxiliary dac enable codes. table 8 shows the auxiliary adc enable code. bits e11 and e10 are reserved. program bits e11 and e10 to logic-low. bits e3, e7, and e8 are not used. modes aux-dac1, aux-dac2, and aux-dac3 select the aux-dac channels named dac1, dac2, and dac3 and hold the data inputs for each dac. bits _d11?d0 are the data inputs for each aux-dac and can be pro- grammed through spi. the MAX19713 also includes two 6-bit registers that can be programmed to adjust the offsets for the tx dac id and qd channels indepen- dently (see table 9). use the comsel mode to select the output common-mode voltage with bits cm1 and cm0 (see table 10). use aux-adc mode to start the auxiliary adc conversion (see the 10-bit, 333ksps auxiliary adc section for details). use enable-8 mode for faster enable and switching between shutdown, idle, and standby states as well as switching between fast, slow, rx and tx modes and the fd mode. the wakeup-sel register selects the operating mode that the MAX19713 is to enter immediately after coming out of shutdown (table 11). see the wake-up function section for more information. shutdown mode offers the most dramatic power savings by shutting down all the analog sections (including the reference) of the MAX19713. in shutdown mode, the rx adc digital outputs are in tri-state mode, the tx dac digital inputs are internally pulled to ov dd , and the tx dac outputs are at 0v. when the rx adc outputs transi- tion from tri-state to active mode, the last converted word is placed on the digital output bus. the tx dac previ- ously stored data is lost when coming out of shutdown mode. the wake-up time from shutdown mode is domi- nated by the time required to charge the capacitors at refp, refn, and com. in internal reference mode and buffered external reference mode, the wake-up time is typically 500? to enter rx mode, 26.4? to enter tx mode, and 500? to enter fd mode. in all operating modes, the tx dac inputs da0?a9 are internally pulled to ov dd . to reduce the supply current of the MAX19713 in shutdown mode do not pull da0?a9 low. this consideration is especially important in shut- down mode to achieve the lowest quiescent current. in idle mode, the reference and clock distribution cir- cuits are powered, but all other functions are off. the rx adc outputs ad0?d9 are forced to tri-state. the tx dac da0?a9 inputs are internally pulled to ov dd , while the tx dac outputs are at 0v. the wake-up time is 3.7? to enter rx mode, 5.1? to enter tx mode, and 5.1? to enter fd mode. when the rx adc outputs transition from tri-state to active, the last converted word is placed on the digital output bus. in standby mode, the reference is powered but all other device functions are off. the wake-up time from stand- by mode is 3.8? to enter rx mode, 24.4? to enter tx mode, and 24.4? to enter fd mode. when the rx adc outputs transition from tri-state to active, the last con- verted word is placed on the digital output bus. fast and slow rx and tx modes the MAX19713 features fast and slow modes for switching between rx and tx operation. in fast tx mode, the rx adc core is powered on but the adc digi- tal outputs ad0?d9 are tri-stated. the tx dac digital bus is active and the dac core is fully operational.
MAX19713 table 4. power-management modes address data bits a3 a2 a1 a0 e9* e2 e1 e0 mode function (power management) description comment 1 0 0 0 shdn shutdown rx adc = off tx dac = off (tx dac outputs at 0v) aux-dac = off aux-adc = off clk = off ref = off device is in complete shutdown. x** 0 0 1 idle idle rx adc = off tx dac = off (tx dac outputs at 0v) aux-dac = last state clk = on ref = on fast turn-on time. moderate idle power. 0000 (16-bit mode) or 1000 (8-bit mode) x** 0 1 0 stby standby rx adc = off tx dac = off (tx dac outputs at 0v) aux-dac = last state clk = off ref = on slow turn-on time. low standby power. x = don? care. * bit e9 is not available in 8-bit mode. ** in idle and stby modes, the aux-adc can be turned on or off. table 3. MAX19713 mode control d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 a3 a2 a1 a0 register name (msb) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 (lsb) enable-16 e11 = 0 reserved e10 = 0 reserved e9 e6 e5 e4 e2 e1 e0 0 0 0 0 aux-dac1 1d11 1d10 1d9 1d8 1d7 1d6 1d5 1d4 1d3 1d2 1d1 1d0 0 0 0 1 aux-dac2 2d11 2d10 2d9 2d8 2d7 2d6 2d5 2d4 2d3 2d2 2d1 2d0 0 0 1 0 aux-dac3 3d11 3d10 3d9 3d8 3d7 3d6 3d5 3d4 3d3 3d2 3d1 3d0 0 0 1 1 ioffset io5 io4 io3 io2 io1 io0 0 1 0 0 qoffset qo5 qo4 qo3 qo2 qo1 qo0 0 1 0 1 comsel cm1 cm0 0 1 1 0 aux-adc ad11 = 0 reserved ad10 ad9 ad8 ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 0 1 1 1 enable-8 e2 e1 e0 1 0 0 0 wakeup-sel w2 w1 w0 1 0 0 1 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 21 = not used.
MAX19713 10-bit, 45msps, full-duplex analog front-end 22 ______________________________________________________________________________________ table 5. MAX19713 tx, rx, and fd control using spi commands in fast rx mode, the tx dac core is powered on. the tx dac outputs are set to midscale. in this mode, the tx dac input bus is disconnected from the dac core and da0?a9 are internally pulled to ov dd . the rx adc dig- ital bus is active and the adc core is fully operational. in fast mode, the switching time from tx to rx, or rx to tx is minimized because the converters are on and do not have to recover from a power-down state. in fast mode, the switching time from rx to tx and tx to rx is 0.1?. power consumption is higher in fast mode because both tx and rx cores are always on. in slow tx mode, the rx adc core is powered off and the adc digital outputs ad0?d9 are tri-stated. the tx dac digital bus is active and the dac core is fully oper- ational. in slow rx mode, the tx dac core is powered off. the tx dac outputs are set to 0. in slow rx mode, the tx dac input bus is disconnected from the dac core and da0?a9 are internally pulled to ov dd . the rx adc digital bus is active and the adc core is fully operational. the switching times for slow modes are 4.9? for rx to tx and 3.7? for tx to rx. power consumption in slow tx mode is 49.5mw, and 79.2mw in slow rx mode. power consumption in fast tx mode is 89.1mw, and 86.4mw in fast rx mode. address data bits a3 a2 a1 a0 e2 e1 e0 mode function (tx-rx switching speed) description comment 0 1 1 spi1-rx slow rx mode: rx adc = on rx bus = enabled tx dac = off (tx dac outputs at 0v) tx bus = off (all inputs are pulled high) slow transition to tx mode from this mode. low power. 1 0 0 spi2-tx slow tx mode: rx adc = off rx bus = tri-state tx dac = on tx bus = on slow transition to rx mode from this mode. low power. 1 0 1 spi3-rx fast rx mode: rx adc = on rx bus = enabled tx dac = on (tx dac outputs at midscale) tx bus = off (all inputs are pulled high) fast transition to tx mode from this mode. moderate power. 1 1 0 spi4-tx fast tx mode: rx adc = on rx bus = tri-state tx dac = on tx bus = on fast transition to rx mode from this mode. moderate power. 0000 (16-bit mode) and 1000 (8-bit mode) 1 1 1 fd fast fd mode: rx adc = on rx bus = on tx dac = on tx bus = on default mode fast transition to any mode. moderate power.
MAX19713 fd mode the MAX19713 features an fd mode, which is ideal for applications supporting frequency-division duplex. in fd mode, both rx adc and tx dac, as well as their respective digital buses, are active and the device can receive and transmit simultaneously. switching from fd mode to other rx or tx modes is fast (0.1?) since table 6. MAX19713 default (power-on) register settings d11 d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 register name 16 (msb) 15 14 13 12 11 10 9 8 7 6 5 0 000 111 enable-16 00 aux- ad c = on aux- d ac1 to aux- d ac3 = on fd mode 011 010001100 aux-dac1 dac1 output set to 1.1v 00 0 0 0 0 0 0 0 0 0 0 aux-dac2 dac2 output set to 0v 00 0 0 0 0 0 0 0 0 0 0 aux-dac3 dac3 output set to 0v 000000 ioffset no offset on channel id 000000 qoffset no offset on channel qd 00 comsel v comd = 1.06v 00 000000000 aux-adc 0 aux-adc = on, conversion = idle, aux-adc ref = 2.048v, mux = adc1, averaging = 1, clock divider = 1, dout = disabled 111 enable-8 fd mode 111 wa keu p- sel wake-up state = fd mode table 7. aux-dac enable table (enable-16 mode) e6 e5 e4 aux-dac3 aux-dac2 aux-dac1 000ononon 001 on on off 010 on off on 011 on off off 1 0 0 off on on 101 off on off 110 off off on 1 1 1 off off off 0 0 0 default mode 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 23 table 8. aux-adc enable table (enable-16 mode) e9 selection 0 (default) aux-adc is powered on 1 aux-adc is powered off
MAX19713 10-bit, 45msps, full-duplex analog front-end 24 ______________________________________________________________________________________ the on-board converters are already powered. consequently, power consumption in this mode is the maximum of all operating modes. in fd mode the MAX19713 consumes 91.8mw. wake-up function the MAX19713 uses the spi interface to control the operating modes of the device including the shutdown and wake-up functions. once the device has been placed in shutdown through the appropriate spi com- mand, the first pulse on cs /wake performs a wake-up function. at the first rising edge of cs /wake, the MAX19713 is forced to a preset operating mode deter- mined by the wakeup-sel register. this mode is termed the wake-up state. if the wakeup-sel register has not been programmed, the wake-up state for the MAX19713 is fd mode by default (tables 6, 11). the wakeup-sel register cannot be programmed with w2 = 0, w1 = 0, and w0 = 0. if this value is inadvertently written to the device, it is ignored and the register con- tinues to store its previous value. upon wake-up, the table 9. offset control bits for id and qd channels (ioffset or qoffset mode) bits io5?o0 when in ioffset mode, bits qo5?o0 when in qoffset mode io5/qo5 io4/qo4 io3/qo3 io2/qo2 io1/qo1 io0/qo0 offset 1 lsb = (vfs p-p / 1023) 111111-31 lsb 111110-30 lsb 111101-29 lsb 100010-2 lsb 100001-1 lsb 1000000mv 0 0 0 0 0 0 0mv (default) 0000011 lsb 0000102 lsb 01110129 lsb 01111030 lsb 01111131 lsb note: 1 lsb = (800mv p-p / 1023) = 0.782mv. table 10. common-mode select (comsel mode) cm1 cm0 tx path output common mode (v) 0 0 1.06 (default) 0 1 0.94 1 0 0.82 1 1 0.71 table 11. wakeup-sel register w2 w1 w0 power mode after wake-up (wake-up state) 000 invalid value . this value is ignored when inadvertently written to the wakeup-sel register. 001 idle 010 stby 0 1 1 spi1-slow rx 1 0 0 spi2-slow tx 1 0 1 spi3-fast rx 1 1 0 spi4-fast tx 111 fd (default)
MAX19713 figure 6. serial-interface timing diagram t csw t cs lsb t cl t cp t ch t dh t ds msb t css sclk din cs/wake 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 25 qspi is a trademark of motorola, inc. figure 7. mode-recovery timing diagram cs/wake sclk din 16-bit serial data input ad0?d9 id/qd dac analog output settles to 10 lsb error adc digital output sinad settles to within 1db t wake,sd,st_ to rx mode or t enable , rx t wake,sd,st_ to tx mode or t enable , tx MAX19713 enters the power mode determined by the wakeup-sel register, however, all other settings (tx dac offset, tx dac common-mode voltage, aux-dac settings, aux-adc state) are restored to their values prior to shutdown. the only spi line that is monitored by the MAX19713 during shutdown is cs /wake. any information transmit- ted to the MAX19713 concurrent with the cs /wake wake-up pulse is ignored. spi timing the serial digital interface is a standard 3-wire connection ( cs /wake, sclk, din) com patible with spi/qspi/ microwire/dsp interfaces. set cs /wake low to enable the serial data loading at din or output at dout. following a cs /wake high-to-low transition, data is shift- ed synchronously, most significant bit first, on the rising edge of the serial clock (sclk). after 16 bits are loaded into the serial input register, data is transferred to the latch when cs /wake transitions high. cs /wake must transi- tion high for a minimum of 80ns before the next write sequence. sclk can idle either high or low between tran- sitions. figure 6 shows the detailed timing diagram of the 3-wire serial interface. mode-recovery timing figure 7 shows the mode-recovery timing diagram. t wake is the wake-up time when exiting shutdown, idle, or standby mode and entering rx, tx, or fd mode. t enable is the recovery time when switching between either rx or tx mode. t wake or t enable is the time for the rx adc to settle within 1db of specified sinad per- formance and tx dac settling to 10 lsb error. t wake and t enable times are measured after the 16-bit serial command is latched into the MAX19713 by a cs /wake transition high. in fast mode, the recovery time is 0.1? to switch between tx or rx modes.
MAX19713 10-bit, 45msps, full-duplex analog front-end 26 ______________________________________________________________________________________ system clock input (clk) both the rx adc and tx dac share the clk input. the clk input accepts a cmos-compatible signal level set by ov dd from 1.8v to v dd . since the interstage con- version of the device depends on the repeatability of the rising and falling edges of the external clock, use a clock with low jitter and fast rise and fall times (< 2ns). specifically, sampling occurs on the rising edge of the clock signal, requiring this edge to provide the lowest possible jitter. any significant clock jitter limits the snr performance of the on-chip rx adc as follows: where f in represents the analog input frequency and t aj is the time of the clock jitter. clock jitter is especially critical for undersampling applications. consider the clock input as an analog input and route away from any analog input or other digital signal lines. the MAX19713 clock input operates with an ov dd / 2 voltage threshold and accepts a 50% ?0% duty cycle. when the clock signal is stopped at clk input (clk = 0 or ov dd ), all internal registers hold their last value and the MAX19713 saves the last power-management mode or tx/rx/fd command. all converter circuits (rx adc, tx dac, aux-adc, and aux-dacs) hold their last value. when the clock signal is restarted at clk, allow 3.8? (clock wake-up time) for the internal clock circuit- ry to settle before updating the tx dac, reading a valid rx adc conversion result, or starting an aux-adc con- version. this ensures the converters (rx adc, tx dac, aux-adc) meet all dynamic performance specifica- tions. the aux-dac channels are not dependent on clk, so they can be updated when clk is idle. 12-bit, auxiliary control dacs the MAX19713 includes three 12-bit aux-dacs (dac1, dac2, dac3) with 1? settling time for controlling vari- able-gain amplifier (vga), automatic gain-control (agc), and automatic frequency-control (afc) func- tions. the aux-dac output range is 0.2v to 2.57v as defined by v oh - v ol . during power-up, the vga and agc outputs (dac2 and dac3) are at zero. the afc dac (dac1) is at 1.1v during power-up. the aux-dacs can be independently controlled through the spi bus, except during shdn mode where the aux-dacs are turned off completely and the output voltage is set to zero. in stby and idle m odes the aux-dacs maintain the last value. on wake-up from shdn, the aux-dacs resume the last values. loading on the aux-dac outputs should be carefully observed to achieve the specified settling time and sta- bility. the capacitive load must be kept to a maximum of 5pf including package and trace capacitance. the resistive load must be greater than 200k . if capacitive loading exceeds 5pf, then add a 10k resistor in series with the output. adding the series resistor helps drive larger load capacitance (< 15pf) at the expense of slower settling time. 10-bit, 333ksps auxiliary adc the MAX19713 integrates a 333ksps, 10-bit aux-adc with an input 4:1 multiplexer. in the aux-adc mode reg- ister, setting bit ad0 begins a conversion with the auxil- iary adc. bit ad0 automatically clears when the conversion is complete. setting or clearing ad0 during a conversion has no effect (see table 12). bit ad1 determines the internal reference of the auxiliary adc (see table 13). bits ad2 and ad3 determine the auxil- iary adc input source (see table 14). bits ad4, ad5, and ad6 select the number of averages taken when a single start-convert command is given. the conversion time increases as the number of averages increases (see table 15). the conversion clock can be divided down from the system clock by properly setting bits ad7, ad8, and ad9 (see table 16). the aux-adc out- put data can be written out of dout by setting bit ad10 high (see table 17). the aux-adc features a 4:1 input multiplexer to allow measurements on four input sources. the input sources are selected by ad3 and ad2 (see table 14). two of the multiplexer inputs (adc1 and adc2) can be con- nected to external sources such as an rf power detec- tor like the max2208 or temperature sensor like the max6613. the other two multiplexer inputs are internal connections to v dd and ov dd that monitor the power- supply voltages. the internal v dd and ov dd connec- tions are made through integrated dividers that yield v dd / 2 and ov dd / 2 measurement results. the aux- adc voltage reference can be selected between an internal 2.048v bandgap reference or v dd (see table 13). the v dd reference selection is provided to allow measurement of an external voltage source with a full- scale range extending beyond the 2.048v level. the input source voltage range cannot extend above v dd . the conversion requires 12 clock edges (1 for input sampling, 1 for each of the 10 bits, and 1 at the end for loading into the serial output register) to complete one conversion cycle (when no averaging is being done). each conversion of an average (when averaging is set greater than 1) requires 12 clock edges. the conver- sion clock is generated from the system clock input (clk). an spi-programmable divider divides the system log snr ft = ? ? ? ? ? ? 20 1 2 in aj
MAX19713 clock by the appropriate divisor (set with bits ad7, ad8, and ad9; see table 16) and provides the conver- sion clock to the auxiliary adc. the auxiliary adc has a maximum conversion rate of 333ksps. the maximum conversion clock frequency is 4mhz (333ksps x 12 clocks). choose the proper divider value to keep the conversion clock frequency under 4mhz, based upon the system clk frequency supplied to the MAX19713 (see table 16). the total conversion time (t conv ) of the auxiliary adc can be calculated as t conv = (12 x n avg x n div ) / f clk ; where n avg is the number of averages (see table 15), n div is the clk divisor (see table 16), and f clk is the system clk frequency. reading dout from the aux-adc dout is normally in a high-impedance condition. upon setting the auxiliary adc start conversion bit (bit ad0), dout becomes active and goes high, indicating that the aux-adc is busy. when the conversion cycle is complete (including averaging), the data is placed into an output register and dout goes low, indicating that the output data is ready to be driven onto dout. when bit ad10 is set (ad10 = 1), the aux-adc enters a data output mode where data is available at dout on the next low assertion of cs /wake. the auxiliary adc data is shifted out of dout (msb first) with the data transi- tioning on the falling edge of the serial clock (sclk). since a dout read requires 16 bits, dout holds the value of the last conversion data bit for the last 6 bits (6 least significant bits) following the aux-adc conversion data. dout enters a high-impedance state when cs /wake is deasserted high. when bit ad10 is cleared (ad10 = 0), the aux-adc data is not available on dout (see table 17). after the aux-adc completes a conversion, the data result is loaded to an output register waiting to be shift- ed out. no further conversions are possible until data is shifted out. this means that if the first conversion com- mand sets ad10 = 0, ad0 = 1, then it cannot be fol- lowed by conversion commands setting ad10 = 0, ad0 = 1 or ad10 = 1, ad0 = 1. if this sequence of com- mands is inadvertently used then dout is disabled. to resume normal operation set ad0 = 0. 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 27 ad1 selection 0 internal 2.048v reference (default) 1 internal v dd reference table 13. auxiliary adc reference table 14. auxiliary adc input source ad3 ad2 aux-adc input source 0 0 adc1 (default) 0 1 adc2 10 v dd / 2 11 ov dd / 2 table 12. auxiliary adc convert ad0 selection 0 aux-adc idle (default) 1 aux-adc start-convert table 15. auxiliary adc averaging table 16. auxiliary adc clock (clk) divider ad6 ad5 ad4 aux-adc averaging 0 0 0 1 conversion (no averaging) (default) 0 0 1 average of 2 conversions 0 1 0 average of 4 conversions 0 1 1 average of 8 conversions 1 0 0 average of 16 conversions 1 0 1 average of 32 conversions 1 1 x average of 32 conversions ad9 ad8 ad7 aux-adc conversion clock 0 0 0 clk divided by 1 (default) 0 0 1 clk divided by 2 0 1 0 clk divided by 4 0 1 1 clk divided by 8 1 0 0 clk divided by 16 1 0 1 clk divided by 32 1 1 0 clk divided by 64 1 1 1 clk divided by 128 x = don? care. table 17. auxiliary adc data output mode ad10 selection 0 aux-adc data is not available on dout (default) 1 aux-adc enters data output mode where data is available on dout
MAX19713 10-bit, 45msps, full-duplex analog front-end 28 ______________________________________________________________________________________ the fastest method to perform sequential conversions with the aux-adc is by sending consecutive commands setting ad10 = 1, ad0 = 1. with this sequence the cs /wake falling edge shifts data from the previous con- version on to dout and the rising edge of cs /wake loads the next conversion command at din. allow enough time for each conversion to complete before sending the next conversion command. see figure 8 for single and continuous conversion examples. figure 8. aux-adc conversions timing cs/wake 2. continuous aux-adc conversions t dcs t conv sclk 00 01 1 11 1 1 001 11 1 1 001 11 16 1 10 11 12 13 14 15 16 1 10 11 12 13 14 15 16 1 din dout d1 d0 d0 held d9 d1 d0 d0 held d9 first 10-bit aux-adc conversion result is shifted out on dout on the falling edge of sclk msb first second 10-bit aux-adc conversion result is shifted out on dout on the falling edge of sclk msb first ad10 = 1, ad0 = 1, perform conversion, dout enabled ad10 = 1, ad0 = 1, perform conversion, dout enabled ad10 = 1, ad0 = 1, perform conversion, dout enabled dout transitions from high impedance to logic- high indicating start of first conversion dout transitions high indicating start of second conversion dout transitions high indicating start of third conversion dout transitions low indicating end of first conversion, data is available and can be shifted out if dout is enabled, ad0 cleared dout transitions low indicating end of second conversion, data is available and can be shifted out if dout is enabled, ad0 cleared dout transitions low indicating end of third conversion, data is available and can be shifted out if dout is enabled, ad0 cleared aux-adc register address t csd t cd t chz cs/wake sclk 1. single aux-adc conversion with conversion data readout at a later time 1 00 1 1 01 00 1 din set high during single read 11 11 16 1 16 1 16 1 16 10 d1 d0 d0 held d9 11 din dout ad10 = 0, ad0 = 1, perform conversion, dout disabled dout transitions from high impedance to logic- high indicating start of conversion dout transitions low indicating end of conversion, data is available and can be shifted out if dout is enabled, ad0 cleared 0 if aux-adc conversion does not need to be read immediately, the spi interface is free and can be used for other functions, such as housekeeping aux-dac adjustment, etc. aux-adc register address conversion result data bit d0 is held for the six least significant bits dout transitions to high impedance 10-bit aux-adc conversion result is shifted out on dout on the falling edge of sclk msb first aux-adc register address ad10 = 1, ad0 = 0, aux-adc idle (no conversion), dout enabled and conversion data is shifted out on next cs/wake falling edge first falling edge of cs/wake after dout is enabled starts shifting the aux-adc conversion data on the falling edge of sclk
MAX19713 din can be written independent of dout state. a 16-bit instruction at din updates the device configuration. to prevent modifying internal registers while reading data from dout, hold din at a high state (only applies if sequential aux-adc conversions are not executed). this effectively writes all ones into address 1111. since address 1111 does not exist, no internal registers are affected. reference configurations the MAX19713 features an internal precision 1.024v- bandgap reference that is stable over the entire power- supply and temperature ranges. the refin input provides two modes of reference operation. the volt- age at refin (v refin ) sets the reference operation mode (table 18). in internal reference mode, connect refin to v dd . v ref is an internally generated 0.512v ?% reference level. com, refp, and refn are low-impedance out- puts with v com = v dd / 2, v refp = v dd / 2 + v ref / 2, and v refn = v dd / 2 - v ref / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in buffered external reference mode, apply 1.024v ?0% at refin. in this mode, com, refp, and refn are low-impedance outputs with v com = v dd / 2, v refp = v dd / 2 + v refin / 4, and v refn = v dd / 2 - v refin / 4. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor. in this mode, the tx dac full-scale output is proportional to the external reference. for example, if the v refin is increased by 10% (max), the tx dac full- scale output is also increased by 10% or ?40mv. applications information using balun transformer ac-coupling an rf transformer (figure 9) provides an excellent solution to convert a single-ended signal source to a fully differential signal for optimum adc performance. connecting the center tap of the transformer to com provides a v dd / 2 dc level shift to the input. a 1:1 transformer can be used, or a step-up transformer can be selected to reduce the drive requirements. in gener- al, the MAX19713 provides better sfdr and thd with fully differential input signals than single-ended signals, especially for high input frequencies. in differential mode, even-order harmonics are lower as both inputs (iap, ian, qap, qan) are balanced, and each of the 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 29 figure 9. balun transformer-coupled single-ended-to- differential input drive for rx adc com iap ian 25 0.1 f 0.33 f 25 0.1 f v in MAX19713 22pf 22pf qap qan 25 0.1 f 0.33 f 25 0.1 f v in 22pf 22pf table 18. reference modes v refin reference mode > 0.8v x v dd internal reference mode. v ref is internally generated to be 0.512v. bypass refp, refn, and com each with a 0.33? capacitor. 1.024v ?0% buffered external reference mode. an external 1.024v ?0% reference voltage is applied to refin. v ref is internally generated to be v refin / 2. bypass refp, refn, and com each with a 0.33? capacitor. bypass refin to gnd with a 0.1? capacitor.
MAX19713 10-bit, 45msps, full-duplex analog front-end 30 ______________________________________________________________________________________ rx adc inputs only requires half the signal swing com- pared to single-ended mode. figure 10 shows an rf transformer converting the MAX19713 tx dac differen- tial analog outputs to single-ended. using op-amp coupling drive the MAX19713 rx adc with op amps when a balun transformer is not available. figures 11 and 12 show the rx adc being driven by op amps for ac-cou- pled single-ended and dc-coupled differential applica- tions. amplifiers such as the max4454 and max4354 provide high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity. the op-amp circuit shown in figure 12 can also be used to interface with the tx dac differential analog outputs to provide gain or buffering. the tx dac differential ana- log outputs cannot be used in single-ended mode because of the internally generated common-mode level. also, the tx dac analog outputs are designed to drive a differential input stage with input impedance 70k . if single-ended outputs are desired, use an amplifier to provide differential-to-single-ended conver- sion and select an amplifier with proper input common- mode voltage range. fdd application figure 13 illustrates a typical fdd application circuit. the MAX19713 interfaces directly with the radio front-ends to provide a complete ?f-to-bits?solution for fdd applica- tions such as 802.11, 802.16, wcdma, and proprietary radio systems. the MAX19713 provides several system benefits to digital baseband developers: fast time-to-market high-performance, low-power analog functions low-risk, proven analog front-end solution no mixed-signal test times no nre charges no ip royalty charges enables digital baseband and scale with 65nm to 90nm cmos grounding, bypassing, and board layout the MAX19713 requires high-speed board layout design techniques. refer to the MAX19713 ev kit data sheet for a board layout reference. place all bypass capacitors as close to the device as possible, preferably on the same side of the board as the device, using surface-mount devices for minimum inductance. bypass v dd to gnd with a 0.1? ceramic capacitor in parallel with a 2.2? capacitor. bypass ov dd to ognd with a 0.1? ceramic figure 11. single-ended drive for rx adc MAX19713 0.1 f 1k 1k 100 100 c in 22pf c in 22pf qap qan com iap ian 0.1 f r iso 50 r iso 50 refp refn v in 0.1 f 1k 1k 100 100 c in 22pf c in 22pf 0.1 f r iso 50 r iso 50 refp refn v in figure 10. balun transformer-coupled differential-to-single- ended output drive for tx dac MAX19713 idp idn v out qdp qdn v out
capacitor in parallel with a 2.2? capacitor. bypass refp, refn, and com each to gnd with a 0.33? ceramic capacitor. bypass refin to gnd with a 0.1? capacitor. multilayer boards with separated ground and power planes yield the highest level of signal integrity. use a split ground plane arranged to match the physical loca- tion of the analog ground (gnd) and the digital output- driver ground (ognd) on the device package. connect the MAX19713 exposed backside paddle to the gnd plane. join the two ground planes at a single point so the noisy digital ground currents do not interfere with the analog ground plane. the ideal location for this connection can be determined experimentally at a point along the gap between the two ground planes. make this connection with a low-value, surface-mount resistor (1 to 5 ), a ferrite bead, or a direct short. alternatively, all ground pins could share the same ground plane, if the ground plane is sufficiently isolated from any noisy digital system? ground plane (e.g., downstream output buffer or dsp ground plane). route high-speed digital signal traces away from sensi- tive analog traces. make sure to isolate the analog input lines to each respective converter to minimize channel-to-channel crosstalk. keep all signal lines short and free of 90 turns. dynamic parameter definitions adc and dac static parameter definitions integral nonlinearity (inl) integral nonlinearity is the deviation of the values on an actual transfer function from a straight line. this straight line can be either a best-straight-line fit or a line drawn between the end points of the transfer function, once offset and gain errors have been nullified. the static lin- earity parameters for the device are measured using the best-straight-line fit (dac figure 14a). MAX19713 figure 12. rx adc dc-coupled differential drive MAX19713 iap com ian r iso 22 r iso 22 r11 600 r9 600 r3 600 r2 600 r1 600 r10 600 r8 600 r5 600 r4 600 r7 600 r6 600 c in 5pf c in 5pf 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 31
MAX19713 10-bit, 45msps, full-duplex analog front-end 32 ______________________________________________________________________________________ figure 13. typical fdd radio application circuit clk serial interface and system control iap ian qap qan idp idn qdp qdn refp com refn dout refin din sclk cs/wake system clock programmable offset/cm 1.024v reference buffer 10-bit adc 10-bit adc 10-bit dac 10-bit dac 12-bit aux-dac 12-bit aux-dac 10-bit aux-adc 12-bit aux-dac gnd v dd / 2 ov dd / 2 dac1 dac2 dac3 adc1 adc2 ognd v dd = 2.7v to 3.3v ov dd = 1.8v to v dd data mux data mux da0 da1 da2 da3 da4 da5 da6 da7 da8 da9 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 MAX19713 digital baseband asic tcxo fdd zif transceiver agc temperature measurement battery voltage monitor
MAX19713 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 33 differential nonlinearity (dnl) differential nonlinearity is the difference between an actual step width and the ideal value of 1 lsb. a dnl error specification of less than 1 lsb guarantees no missing codes (adc) and a monotonic transfer function (adc and dac) (dac figure 14b). adc offset error ideally, the midscale transition occurs at 0.5 lsb above midscale. the offset error is the amount of deviation between the measured transition point and the ideal transition point. dac offset error offset error (figure 14a) is the difference between the ideal and actual offset point. the offset point is the out- put value when the digital input is midscale. this error affects all codes by the same amount and usually can be compensated by trimming. adc gain error ideally, the adc full-scale transition occurs at 1.5 lsb below full scale. the gain error is the amount of devia- tion between the measured transition point and the ideal transition point with the offset error removed. adc dynamic parameter definitions aperture jitter figure 15 shows the aperture jitter (t aj ), which is the sample-to-sample variation in the aperture delay. aperture delay aperture delay (t ad ) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (figure 15). signal-to-noise ratio (snr) for a waveform perfectly reconstructed from digital samples, the theoretical maximum snr is the ratio of the full-scale analog input (rms value) to the rms quantization error (residual error) and results directly from the adc? resolution (n bits): snr(max) = 6.02 x n + 1.76 (in db) in reality, there are other noise sources besides quanti- zation noise: thermal noise, reference noise, clock jitter, etc. snr is computed by taking the ratio of the rms signal to the rms noise. rms noise includes all spec- tral components to the nyquist frequency excluding the fundamental, the first five harmonics, and the dc offset. signal-to-noise and distortion (sinad) sinad is computed by taking the ratio of the rms sig- nal to the rms noise. rms noise includes all spectral components to the nyquist frequency excluding the fundamental and the dc offset. hold analog input sampled data (t/h) t/h t ad t aj track track clk figure 15. t/h aperture timing 0 2 1 4 3 7 6 5 000 010 001 011 100 101 110 at step 011 (0.5 lsb) at step 001 (0.25 lsb) 111 digital input code analog output value figure 14a. integral nonlinearity 0 2 1 4 3 6 5 000 010 001 011 100 101 differential linearity error (-0.25 lsb) differential linearity error (+0.25 lsb) 1 lsb 1 lsb digital input code analog output value figure 14b. differential nonlinearity
MAX19713 10-bit, 45msps, full-duplex analog front-end 34 ______________________________________________________________________________________ effective number of bits (enob) enob specifies the dynamic performance of an adc at a specific input frequency and sampling rate. an ideal adc? error consists of quantization noise only. enob for a full-scale sinusoidal input waveform is computed from: enob = (sinad - 1.76) / 6.02 total harmonic distortion (thd) thd is typically the ratio of the rms sum of the first five harmonics of the input signal to the fundamental itself. this is expressed as: where v 1 is the fundamental amplitude and v 2 ? 6 are the amplitudes of the 2nd- through 6th-order harmonics. third harmonic distortion (hd3) hd3 is defined as the ratio of the rms value of the third harmonic component to the fundamental input signal. spurious-free dynamic range (sfdr) sfdr is the ratio expressed in decibels of the rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest spurious com- ponent, excluding dc offset. intermodulation distortion (imd) imd is the total power of the intermodulation product rel- ative to the total input power when two tones, f in1 and f in2 , are present at the inputs. the intermodulation prod- ucts are (f in1 ? in2 ), (2 x f in1 ), (2 x f in2 ), (2 x f in1 f in2 ), (2 x f in2 ? in1 ). the individual input tone levels are at -7dbfs. 3rd-order intermodulation (im3) im3 is the power of the worst 3rd-order intermodulation product relative to the input power of either input tone when two tones, f in1 and f in2 , are present at the inputs. the 3rd-order intermodulation products are (2 x f in1 f in2 ), (2 ? f in2 ? in1 ). the individual input tone levels are at -7dbfs. power-supply rejection power-supply rejection is defined as the shift in offset and gain error when the power supply is changed ?%. small-signal bandwidth a small -20dbfs analog input signal is applied to an adc in such a way that the signal? slew rate does not limit the adc? performance. the input frequency is then swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. note that the t/h performance is usually the limiting factor for the small-signal input bandwidth. full-power bandwidth a large -0.5dbfs analog input signal is applied to an adc, and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by 3db. this point is defined as the full- power bandwidth frequency. dac dynamic parameter definitions total harmonic distortion thd is the ratio of the rms sum of the output harmonics up to the nyquist frequency divided by the fundamental: where v 1 is the fundamental amplitude and v 2 through v n are the amplitudes of the 2nd through nth harmonic up to the nyquist frequency. spurious-free dynamic range spurious-free dynamic range (sfdr) is the ratio of rms amplitude of the fundamental (maximum signal compo- nent) to the rms value of the next-largest distortion component up to the nyquist frequency excluding dc. thd (v + v + ...+ v ) v 2 2 3 2 n 2 1 = ? ? ? ? ? ? ? ? 20 x log thd (v +v +v +v +v ) v 2 2 3 2 4 2 5 2 6 2 1 = ? ? ? ? ? ? ? ? 20 x log selector guide part sampling rate (msps) integrated cdma tx filters max19710 7.5 no max19711 11 yes max19712 22 no MAX19713 45 no
MAX19713 10-bit, 45msps, full-duplex analog front-end ______________________________________________________________________________________ 35 clk serial interface and system control iap ian qap qan idp idn qdp qdn refp refn com dout refin din sclk cs/wake system clock programmable offset/cm 1.024v reference buffer 10-bit adc 10-bit adc 10-bit dac 10-bit dac 12-bit aux-dac 12-bit aux-dac 12-bit aux-dac gnd v dd / 2 ov dd / 2 dac1 dac2 dac3 adc1 10-bit aux-adc adc2 ognd v dd = 2.7v to 3.3v ov dd = 1.8v to v dd data mux data mux da0 da1 da2 da3 da4 da5 da6 da7 da8 da9 ad0 ad1 ad2 ad3 ad4 ad5 ad6 ad7 ad8 ad9 MAX19713 functional diagram
MAX19713 10-bit, 45msps, full-duplex analog front-end 36 ______________________________________________________________________________________ 32, 44, 48l qfn .eps e l e l a1 a a2 e/ 2 e d/2 d detail a d2/2 d2 b l k e2/2 e2 (ne-1) x e (nd-1) x e e c l c l c l c l k package outline 21-0144 2 1 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m package information (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .)
MAX19713 10-bit, 45msps, full-duplex analog front-end maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circu it patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 ____________________ 37 2006 maxim integrated products is a registered trademark of maxim integrated products, inc. package inform ation (continued) (the package drawing(s) in this data sheet may not reflect the most current specifications. for the latest package outline info rmation, go to www.maxim-ic.com/packages .) package outline 21-0144 2 2 f 32, 44, 48, 56l thin qfn, 7x7x0.8m m springer revision history pages changed at rev 1: 1?, 29, 37

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